A MPEG-4 video LSI with an error-resilient codec core based on a fast motion estimation algorithm

Digest of Technical Papers - IEEE International Solid-State Circuits Conference

Volumn , Issue SUPPL., 2002, Pages 296-297+511

  Nakayama, Hiroshi ^a   Yoshitake, Toshiyuki ^a   Komazaki, Hiroshi ^a   Watanabe, Yasuhiro ^a   Araki, Hisakatsu ^a   Morioka, Kiyonori ^a   Li, Jiang ^a   Peilin, Liu ^a   Lee, Shinhaeng ^a   Kubosawa, Hajime ^a   Otobe, Yukio ^a  

^a FUJITSU LABORATORIES LTD   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

ALGORITHMS; CACHE MEMORY; CHIP SCALE PACKAGES; CMOS INTEGRATED CIRCUITS; DIGITAL SIGNAL PROCESSING; IMAGE CODING; IMAGE QUALITY; MOTION ESTIMATION; MOTION PICTURES; PIPELINE PROCESSING SYSTEMS;

CLOCK GATING; QUAD-METAL TECHNOLOGY; VIDEO CODEC;

LSI CIRCUITS;

EID: 0036231772     PISSN: 01936530     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (0)