An on-chip 3 MB subarray-based 3rd level cache on an itanium microprocessor

Digest of Technical Papers - IEEE International Solid-State Circuits Conference

Volumn , Issue SUPPL., 2002, Pages 88-89+413

  Weiss, Don ^a   Wuu, John J ^a   Chin, Victor ^a  

^a HEWLETT PACKARD COMPANY   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

BANDWIDTH; DATA TRANSFER; DECODING; FEEDBACK; FLIP FLOP CIRCUITS; GATES (TRANSISTOR); INTEGRATED CIRCUIT LAYOUT; MICROPROCESSOR CHIPS; RANDOM ACCESS STORAGE;

FULLY CUSTOM CELLS; SUBARRAY DESIGN;

CACHE MEMORY;

EID: 0036226969     PISSN: 01936530     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (0)