Design of a low-cost integrated 0.25 μm CMOS Bluetooth SOC in 16.5 mm2 silicon area

Digest of Technical Papers - IEEE International Solid-State Circuits Conference

Volumn , Issue SUPPL., 2002, Pages 68-69+403

  Cheah, Jonathon ^a   Kwek, Ee Hong ^a   Low, Eng Chuan ^a   Quek, Chee Kwang ^a   Yong, Christopher ^a   Enright, Roy ^a   Hirbawi, Jacob ^a   Lee, Andrew ^a   Xie, Hongyu ^a   Wei, Longyin ^a   Luong, Le ^a   Pan, Jianping ^a   Yang, Shih Tsung ^a   Lau, Wing Fat Andy ^a   Ngai, Wai Lim ^a  

^a Transilica Inc   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

BANDWIDTH; CHIP SCALE PACKAGES; COCHANNEL INTERFERENCE; COST EFFECTIVENESS; ELECTRIC POWER UTILIZATION; MULTICARRIER MODULATION; SEMICONDUCTING SILICON;

POWER CONSUMPTION;

CMOS INTEGRATED CIRCUITS;

EID: 0036226763     PISSN: 01936530     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (0)