Optimum control design of PWM-Buck topologies to minimize output impedance

Conference Proceedings - IEEE Applied Power Electronics Conference and Exposition - APEC

Volumn 1, Issue , 2002, Pages 426-432

  Soto, A ^a   Alou, P ^a   Oliver, J A ^a   Cobos, J A ^a   Uceda, J ^a  

^a UNIVERSIDAD POLITÉCNICA DE MADRID   (Spain)

Author keywords

[No Author keywords available]

Indexed keywords

CLOSED LOOP CONTROL SYSTEMS; ELECTRIC CONTROL EQUIPMENT; ELECTRIC IMPEDANCE; ELECTRIC LOADS; OPTIMAL CONTROL SYSTEMS; OPTIMIZATION; PULSE WIDTH MODULATION; ROOT LOCI; TIME DOMAIN ANALYSIS;

OPTIMUM CONTROL DESIGN;

VOLTAGE CONTROL;

EID: 0036079588     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (5)

1. Analysis and optimization of synchronous buck converter at high Slew-rate load current transients
2. Optimizing the load transient response of the buck converter
3. Design considerations for low-voltage on-board DC/DC modules for next generations of data processing circuits
4. Design optimization of switched mode power supplies (SMPS) feedback control