A robust high voltage Si LDMOS model extraction process to achieve first pass linear RFIC amplifier design success

IEEE MTT-S International Microwave Symposium Digest

Volumn 1, Issue , 2002, Pages 263-266

  Plà, Jaime A ^a   Bridges, Daren ^a  

^a MOTOROLA INC   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ELECTRIC POTENTIAL; FIELD EFFECT TRANSISTORS; INTEGRATED CIRCUIT LAYOUT; ISOTHERMS; MATHEMATICAL MODELS; MOS DEVICES; POWER AMPLIFIERS; RADIO FREQUENCY AMPLIFIERS; SCATTERING PARAMETERS; SEMICONDUCTING SILICON; SPURIOUS SIGNAL NOISE; TEMPERATURE;

LINEAR POWER AMPLIFIERS; RADIO FREQUENCY INTEGRATED CIRCUITS AMPLIFIER;

LINEAR INTEGRATED CIRCUITS;

EID: 0036076196     PISSN: 0149645X     EISSN: None     Source Type: Journal    
DOI: 10.1109/MWSYM.2002.1011607     Document Type: Article

References (4)

1. Characterization and modeling of high power RF semiconductor devices under constant and pulsed excitations
2. Technology-independent large-signal FET models: A measurement-based approach to active device modeling
3. High power device modeling and characterization of high voltage Si LDMOS under constant and pulsed conditions
4. A new dynamic electro-thermal nonlinear model for silicon RF LDMOS FETs