A simulation study on periodical priority dispatching of WIP for product-mix fabrication

IEEE International Symposium on Semiconductor Manufacturing Conference, Proceedings

Volumn , Issue , 2002, Pages 33-37

  Saito, Kazuyuki ^a   Arima, Sumika ^a  

^a UNIVERSITY OF AIZU   (Japan)

Author keywords

Cycle time; Dispatching; Product mix; Utilization; VLSI manufacturing

Indexed keywords

ALGORITHMS; COMPUTER SIMULATION; MONTE CARLO METHODS; VLSI CIRCUITS;

BOTTLENECKED PROCESSING STEP; CYCLE TIME; NON-BOTTLENECKED PROCESSING STEP; PRODUCT-MIX FABRICATION; PSEUDO PERIODICAL PRIORITY DISPATCHING; UTILIZATION; WORK-IN-PROGRESS;

SEMICONDUCTOR DEVICE MANUFACTURE;

EID: 0036075897     PISSN: 1523553X     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (3)