A novel asymmetric gate recess process for InP HEMTs

Conference Proceedings-International Conference on Indium Phosphide and Related Materials

Volumn , Issue , 2002, Pages 221-224

  Robin, Franck ^a   Meier, Hanspeter ^a   Homan, Otte J ^a   Bächtold, Werner ^a  

^a ETH ZURICH   (Switzerland)

Author keywords

[No Author keywords available]

Indexed keywords

DEGRADATION; ELECTRIC BREAKDOWN; ELECTRON BEAM LITHOGRAPHY; GATES (TRANSISTOR); SEMICONDUCTING INDIUM PHOSPHIDE;

ASYMMETRIC GATE RECESS PROCESS;

HIGH ELECTRON MOBILITY TRANSISTORS;

EID: 0036047874     PISSN: 10928669     EISSN: None     Source Type: Journal    
DOI: 10.1109/ICIPRM.2002.1014332     Document Type: Article

References (7)

1. On-state and off-state breakdown in GaInAs/InP composite-channel HEMTs with variable GaInAs channel thickness
2. Single step lithography for double-recessed gate pseudomorphic high electron mobility transistors
3. Multilayer resist process for asymmetric gate recess in field-effect transistors
4. Physics and behavior of asymmetrically recessed InP-based MODFET's fabricated with an electron beam resist process
5. Evolutionary optimization of the electron-beam lithography process for gate fabrication of HEMTs
6. Simulation and evolutionary optimization of electron-beam lithography with genetic and simplex-downhill algorithms
7. A new gate current extraction technique for measurement of on-state breakdown voltage in HEMTs