Lateral 10-15V DMOST with very low 6 mOhm.mm2 on-resistance

IEEE International Symposium on Power Semiconductor Devices and ICs (ISPSD)

Volumn , Issue , 2002, Pages 301-304

  Ludikhuize, Adriaan W ^a  

^a PHILIPS RESEARCH LABORATORIES   (Netherlands)

Author keywords

[No Author keywords available]

Indexed keywords

DC MACHINERY; ELECTRIC BREAKDOWN; ELECTRIC POTENTIAL; ELECTRIC RECTIFIERS; OXIDATION; POWER CONVERTERS; SUBSTRATES; TRANSCONDUCTANCE;

EPITAXIAL LAYERS;

MOSFET DEVICES;

EID: 0036045604     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (15)

1. Power management for future microprocessors
2. 0.6um BiCMOS-based 15 and 25V LDMOS
3. LDMOS in 0.35um BCD technology BCD-6
4. 0.35um CMOS-based smart power 7-50V
5. New adaptive Resurf for 20V LDMOS
6. 0.35um (vertical) trench MOST (18 mOhm.mm2, 32V)
7. Improved 20V lateral trench-gate power MOST 7.8mO.mm2
8. Self-aligned and shielded-resurf 20V LDMOS
9. Hot-electron and trapping in sub-micron DMOST
10. 0.35um 4.3mOhm.mm2, 6mOhm power MOST
11. A-BCD, an economic 100V Resurf-SOI technology
12. Extended 180V voltage in 0.6um thin-layer-SOI A-BCD-technology
13. Optimization of switching performance for LV n-ch trench-MOST