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1
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0001827834
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Enabling alternating phase shifted mask designs for a full logic gate level
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March
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L. Liebmann, J. Lund, F. Heng, I. Graur, "Enabling alternating phase shifted mask designs for a full logic gate level," J. Microlith., Microfab., Microsyst., Vol. 1 No. 1, March 2002.
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(2002)
J. Microlith., Microfab., Microsyst.
, vol.1
, Issue.1
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Liebmann, L.1
Lund, J.2
Heng, F.3
Graur, I.4
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3
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0000728551
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Optical proximity correction for intermediate pitch features using sub resolution scattering bars
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Nov. Dec
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C.J. Chen, T. Laidig, K.E. Wampler, R. Caldwell, "Optical proximity correction for intermediate pitch features using sub resolution scattering bars," J. Vac. Sci. Technol. B, Microelectron. Nanometer Struct. (USA) Vol. 15, No.6 Nov. Dec. 1997 P2426-33.
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J. Vac. Sci. Technol. B, Microelectron. Nanometer Struct. (USA)
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, pp. 2426-2433
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Chen, C.J.1
Laidig, T.2
Wampler, K.E.3
Caldwell, R.4
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4
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0003297501
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Assist features-Challenges and opportunities
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J. Bruce, M. Cross, L. Liebmann, S. Mansfield, and A. McGuire, "Assist Features-Challenges and Opportunities", ARCH Microlithography Symposium, (2000).
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(2000)
ARCH Microlithography Symposium
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Bruce, J.1
Cross, M.2
Liebmann, L.3
Mansfield, S.4
McGuire, A.5
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5
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0020249292
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Improving resolution in photolithography with a phase-shifting mask
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Dec
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M. Levinson, N. Viswanathan, and R. Simpson, "Improving resolution in photolithography with a phase-shifting mask," IEEE Transactions on Electron Devices, vol. 29, pp. 1812-1846, Dec. 1982.
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IEEE Transactions on Electron Devices
, vol.29
, pp. 1812-1846
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Levinson, M.1
Viswanathan, N.2
Simpson, R.3
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6
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0035465564
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TCAD development for lithography resolution enhancement
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September
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L. Liebmann, S. Mansfield, A. Wong, M. Lavin, W. Leipold, T. Dunham, "TCAD development for lithography resolution enhancement," IBM Journal of Research and Development v.45 n.5 September 2001 p.651-665.
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(2001)
IBM Journal of Research and Development
, vol.45
, Issue.5
, pp. 651-665
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Liebmann, L.1
Mansfield, S.2
Wong, A.3
Lavin, M.4
Leipold, W.5
Dunham, T.6
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7
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18644385860
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Sub-resolution assist feature implementation for high performance logic gate-level lithography
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A. Gabor et al., "Sub-resolution Assist Feature Implementation for High Performance Logic Gate-Level Lithography," to be published in Proc. SPIE vol. 4691 (2002).
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(2002)
Proc. SPIE
, vol.4691
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Gabor, A.1
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9
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0001588746
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Optimizing style options for sub-resolution assist features
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C. Progler, ed., SPIE
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L. Liebmann, S. Mansfield, J. Bruce, M. Cross, I. Graur, A. McGuire, J. Krueger, D. Sunderling, "Optimizing style options for sub-resolution assist features," in Proc. SPIE (C. Progler, ed.), vol 4346, SPIE, 2001.
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(2001)
Proc. SPIE
, vol.4346
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Liebmann, L.1
Mansfield, S.2
Bruce, J.3
Cross, M.4
Graur, I.5
McGuire, A.6
Krueger, J.7
Sunderling, D.8
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10
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0036031213
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RET compliant cell generation for sub-130 nm processes
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J.A. Torres, D. Chow, P. deDood, D.J. Albers, "RET Compliant Cell Generation for sub-130nm Processes," to be published in Proc. SPIE vol. 4692 (2002).
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(2002)
Proc. SPIE
, vol.4692
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Torres, J.A.1
Chow, D.2
DeDood, P.3
Albers, D.J.4
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11
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0000327680
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170 nm gates fabricated by phase shift mask and top anti-reflector process
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T. Brunner et al., "170nm gates fabricated by phase shift mask and top anti-reflector process", SPIE 1927, p. 16, (1993).
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(1993)
SPIE
, vol.1927
, pp. 16
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Brunner, T.1
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12
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0029520956
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Phase edge lithography for sub-0.1um electrical channel length in a 200 mm full cmos process
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No. 95CH35781
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P. Agnello, T. Newman, E. Crabbe, S. Subbanna, E. Ganin, L. Liebmann, J. Comfort, D. Sunderland, "Phase edge lithography for sub-0.1um electrical channel length in a 200mm full cmos process," VLSI Symposium IEEE Cat. No. 95CH35781, p. 79, (1995).
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(1995)
VLSI Symposium IEEE Cat.
, pp. 79
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Agnello, P.1
Newman, T.2
Crabbe, E.3
Subbanna, S.4
Ganin, E.5
Liebmann, L.6
Comfort, J.7
Sunderland, D.8
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13
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0034848378
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Enabling alternating phase shifted mask designs for a full logic gate level: Design rules and design rule checking
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IEEE cat n.01CH37232
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L. Liebmann, J. Lund, F. Heng, I. Graur, "Enabling alternating phase shifted mask designs for a full logic gate level: Design rules and design rule checking," 38th Design Automation Conference. Proceedings-Design Automation Conference 2001 p.79-84 (IEEE cat n.01CH37232).
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(2001)
38th Design Automation Conference. Proceedings-Design Automation Conference 2001
, pp. 79-84
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Liebmann, L.1
Lund, J.2
Heng, F.3
Graur, I.4
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14
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84949795280
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New graph bipartizations for double exposure, bright field alternating phase shift mask layout
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Cat. No.01EX455
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A.B. Kahng, S. Vaya, A. Zelikovsky, "New graph bipartizations for double exposure, bright field alternating phase shift mask layout," Proceedings of the ASP DAC 2001. Asia and South Pacific Design Automation Conference 2001 (Cat. No.01EX455) 2001 P133-8.
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(2001)
Proceedings of the ASP DAC 2001. Asia and South Pacific Design Automation Conference 2001
, pp. 133-138
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Kahng, A.B.1
Vaya, S.2
Zelikovsky, A.3
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15
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0003960304
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US Patent No. 5,923,566 (July)
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G. Galan, I. Graur, L. Liebmann, "Phase shifted design verification routine," US Patent No. 5,923,566 (July 1999).
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(1999)
Phase shifted design verification routine
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Galan, G.1
Graur, I.2
Liebmann, L.3
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17
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0036031542
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Exposing the DUV SCAAM-75 nm imaging on the cheap!
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M.D. Levenson, T. Ebihara, "Exposing the DUV SCAAM-75nm Imaging on the Cheap!," to be published in Proc. SPIE vol. 4692 (2002).
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(2002)
Proc. SPIE
, vol.4692
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Levenson, M.D.1
Ebihara, T.2
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