Skewing clock to decide races- double-edge-triggered flip-flop

Electronics Letters

Volumn 37, Issue 25, 2001, Pages 1506-1507

  Varma, P ^a   Ramganesh, K N ^a  

^a INDIAN INSTITUTE OF TECHNOLOGY DELHI   (India)

Author keywords

[No Author keywords available]

Indexed keywords

CAPACITORS; ELECTRIC INVERTERS; FEEDBACK; FREQUENCIES; GATES (TRANSISTOR); TIMING CIRCUITS; TRIGGER CIRCUITS;

DOUBLE-EDGE-TRIGGERED FLIP-FLOPS;

FLIP FLOP CIRCUITS;

EID: 0035818844     PISSN: 00135194     EISSN: None     Source Type: Journal    
DOI: 10.1049/el:20011036     Document Type: Article

References (4)

1. Reduced implementation of D-type DET flip-flops
2. Low-power double-edge triggered flipflop
3. Low power design using double edge triggered flip-flops
4. Accurate simulation of power dissipation in VLSI circuits