Controlled power/ground noise on multi-layer digital printed circuit board using adaptive CMOS output driving scheme

IEEE International Symposium on Electromagnetic Compatibility

Volumn 2, Issue , 2001, Pages 921-926

  Kim, Hyungsoo ^a   Ryu, Woonghwan ^a   Kim, Jonghoon ^a   Kim, Joungho ^a  

^a Korea Advanced Institute of Science and Technology (KAIST)   (South Korea)

Author keywords

[No Author keywords available]

Indexed keywords

CMOS INTEGRATED CIRCUITS; ELECTRIC POTENTIAL; POWER CONTROL; SPURIOUS SIGNAL NOISE; SWITCHING;

OUTPUT DRIVING SCHEMES;

PRINTED CIRCUIT BOARDS;

EID: 0035785279     PISSN: 01901494     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (3)

1. C. S. Choy, et al., "A Low Power-Noise Output Driver with an Adaptive Characteristic Applicable to a Wide Range of Loading Conditions", BEEE JSSC, Vol. 32, No. 6, pp. 913-917 June, 1997
2. Tomonori Sekiguchi et al., "Low-Noise, High-Speed Data Transmission Using a Ringing-Canceling Output Buffer", IEEE JSSC, vol. 30, no. 12, Dec. 1995
3. T.J. Gabara, at el. "Digitally Adjustable Resistors in CMOS for High-performance Applications", IEEE JSSC, vol. 27, no. 8, August 1992