A network processor architecture for flexible QoS control in very high-speed line interfaces

2001 IEEE Workshop on High Performance Switching and Routing

Volumn , Issue , 2001, Pages 402-406

  Shimonishi, Hideyuki ^a   Murase, Tutomu ^a  

^a NEC CORPORATION   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

PACKET NETWORKS; QUALITY OF SERVICE; QUEUEING NETWORKS; ROUTERS; SWITCHING SYSTEMS; USER INTERFACES;

HIGH SPEED LINE INTERFACES; NETWORK PROCESSOR ARCHITECTURE; PACKET SCHEDULING; QUEUEING SCHEDULING;

PIPELINE PROCESSING SYSTEMS;

EID: 0035785104     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (7)

1. "Intel IXP1200 Network Processor", available at http://developer.intel.com/design/network/products/npfamily/ixp1200.htm
2. "IBM network processor product overview", available at http://www.chips.ibm.com/products/commun/documents/netpr_appnote_02_110499.pdf
3. F. Baker, "Requirements for IP version 4 router", IETF RFC-1812, June 1995.
4. J. Heinanen, "Multiprotocol Encapsulation over ATM Adaptation Layer 5", IETF RFC-1483, Jul. 1993.
5. M. Laubach and J. Halpern, "Classical IP and ARP over ATM", IETF RFC-2225, 1998.
6. H. Shimonishi, Tutomu Murase, and Kenji Yamada, "IP-on-the-fly Packet Processing Mechanism for an ATM/IP Integrated Switch", Globecom'99, Dec. 1999.
7. M. Katavanis, S. Sidiropoulos, and C. Courcoubetis, "Weighted Round-Robin Cell Multiplexing in a General-Purpose ATM Switch Chip", IEEE Journal on Selected Areas in Communication, Vol.9, No.8, 1991.