FPGA implementation of IS-95 CDMA baseband filter

International Conference on ASIC, Proceedings

Volumn , Issue , 2001, Pages 411-415

  Lian, Yong ^a   Hwee, Poh Meng ^a  

^a NATIONAL UNIVERSITY OF SINGAPORE   (Singapore)

Author keywords

[No Author keywords available]

Indexed keywords

CODE DIVISION MULTIPLE ACCESS; FIELD PROGRAMMABLE GATE ARRAYS; FREQUENCY MULTIPLYING CIRCUITS; PULSE SHAPING CIRCUITS;

FREQUENCY RESPONSE MASKING; INTERPOLATED FINITE IMPULSE RESPONSE; PULSE SHAPING FILTER;

FIR FILTERS;

EID: 0035721261     PISSN: None     EISSN: None     Source Type: Journal    
DOI: None     Document Type: Conference Paper

References (12)

1. FPGA implementation of digital filters
2. Efficient FIR filter architecture suitable for FPGA implementation
3. FPGA implementation of FIR filters using pipelined bit-serial canonical signed digit multipliers
4. FPGA implementation of high performance FIR filters
5. Efficient filter design for IS-95 CDMA Systems
6. 1:N interpolation FIR filter design for SSB/BPSK-DS/CDMA
7. Pulse-shaping filter design for SSB/BPSK-DS/CDMA using look-up table
8. Interpolated finite impulse response filters
9. Frequency response masking approach for the synthesis of sharp linear phase digital filter
10. The optimum design of 1-D and 2-D FIR filters using frequency response masking technique
11. Frequency response masking approach for digital filter design : Complexity reduction via masking filter factroisation
12. FIR filter design over a discrete powers-of-two coefficient space