A fine-grain asynchronous pipeline reaching the synchronous speed

International Conference on ASIC, Proceedings

Volumn , Issue , 2001, Pages 547-550

  Choy, Chiu sing ^a   Butas, Jan ^a   Povazanec, Juraj ^a   Chan, Cheong fat ^a  

^a NONE

Author keywords

[No Author keywords available]

Indexed keywords

ENCODING (SYMBOLS); LOGIC DESIGN; PARALLEL PROCESSING SYSTEMS; REDUCED INSTRUCTION SET COMPUTING;

LOCALLY DISTRIBUTED ASYNCHRONOUS PIPELINE; PARITY ENCODER;

APPLICATION SPECIFIC INTEGRATED CIRCUITS;

EID: 0035719555     PISSN: None     EISSN: None     Source Type: Journal    
DOI: None     Document Type: Conference Paper

References (8)

1. Analyzing cycle stealing on synchronous circuits with level-sensitive latches
2. Micropipelines
3. Bubbles can make self-timed pipelines fast
4. Design and implementation of an asynchronous microprocessor
5. Micropipelined ARM
6. Cascode voltage switch logic: A differential CMOS logic family
7. High performance asynchronous pipeline circuits