ASICosyn: Co-synthesis of conditional task graphs with custom ASICs

International Conference on ASIC, Proceedings

Volumn , Issue , 2001, Pages 130-135

  Xie, Yuan ^a   Wolf, Wayne ^a  

^a Princeton University   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ALGORITHMS; COMPUTER ARCHITECTURE; COMPUTER HARDWARE; COMPUTER HARDWARE DESCRIPTION LANGUAGES; DISTRIBUTED COMPUTER SYSTEMS; EMBEDDED SYSTEMS; RESOURCE ALLOCATION;

BEHAVIORAL LEVEL ARCHITECTURAL EXPLORATION SYSTEM; CO-SYNTHESIS; CONDITIONAL TASK GRAPHS; DISTRIBUTED REAL TIME EMBEDDED SYSTEMS;

APPLICATION SPECIFIC INTEGRATED CIRCUITS;

EID: 0035719414     PISSN: None     EISSN: None     Source Type: Journal    
DOI: None     Document Type: Conference Paper

References (12)

1. Hardware/software co-design of heterogeneous real-time distributed embedded systems
2. TGFF: Task graphs for free
3. MOGAC: A multiobjective genetic algorithm for HW/SW cosynthesis of hierarchical heterogeneous distributed embedded systems
4. Scheduling of conditional process graphs for the synthesis of embedded systems
5. Embedded system synthesis by timing constraint solving
6. Hardware-software co-synthesis of embedded real-time multiprocessors
7. Monet reference manual
8. SOS: Synthesis of application specific heterogeneous multiprocessor systems
9. An architectural co-synthesis algorithm for distributed, embedded computing systems
10. Co-synthesis with custom ASICs
11. Allocation and scheduling of conditional task graph in hardware/software co-synthesis