Integration of porous ultra low-k dielectric with CVD barriers

Technical Digest-International Electron Devices Meeting

Volumn , Issue , 2001, Pages 88-91

  Mosig, K ^a   Cox, H ^a,b   Klawuhn, E ^c   Suwwan De Felipe, T ^c   Shiota, A ^d  

^a INFINEON TECHNOLOGIES AG   (Germany)

^b PHILIPS RESEARCH LABORATORIES   (Netherlands)

^c Novellus Systems   (United States)

^d JSR CORPORATION   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

CHEMICAL VAPOR DEPOSITION; DIELECTRIC MATERIALS; LEAKAGE CURRENTS; PERMITTIVITY; PORE SIZE; POROSITY; POROUS MATERIALS; SCANNING ELECTRON MICROSCOPY; SEMICONDUCTOR DEVICE STRUCTURES; TITANIUM NITRIDE; TRANSMISSION ELECTRON MICROSCOPY;

CHEMICAL VAPOR DEPOSITION BARRIER; DUAL DAMASCENE STRUCTURES;

INTEGRATED CIRCUIT MANUFACTURE;

EID: 0035717182     PISSN: 01631918     EISSN: None     Source Type: Journal    
DOI: 10.1109/IEDM.2001.979416     Document Type: Article

References (5)

1. Single and dual damascene integration of a spin on porous ultra low-k material
2. Dual hard mask process for low-k porous organosilica dielectric in copper dual damascene interconnect fabrication
3. Evaluation of amorphous (Mo, Ta, W)-Si-N diffusion barriers for [Si]/Cu metallizations
4. MOCVD TiN diffusion barriers for copper interconnects