SoC CMOS technology for NBTI/HCI immune I/O and analog circuits implementing surface and buried channel structures

Technical Digest - International Electron Devices Meeting

Volumn , Issue , 2001, Pages 869-872

  Nishida, Y ^a   Sayama, H ^a   Ohta, K ^a   Oda, H ^a   Katayama, M ^a   Inoue, Y ^a   Morimoto, H ^a   Inuishi, M ^a  

^a MITSUBISHI ELECTRIC CORPORATION   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

INPUT OUTPUT PROGRAMS; MOSFET DEVICES; RELIABILITY; SEMICONDUCTOR DEVICE MANUFACTURE; TEMPERATURE;

ANALOG CIRCUITS; HOT CARRIER INJECTION; NEGATIVE BIAS TEMPERATURE INSTABILITY; SURFACE CHANNEL; SYSTEM ON A CHIP;

CMOS INTEGRATED CIRCUITS;

EID: 0035714856     PISSN: 01631918     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (5)