Impact of 0.25μm dual gate oxide thickness CMOS process on flicker noise performance of multifingered deep-submicron MOS devices

IEE Proceedings: Circuits, Devices and Systems

Volumn 148, Issue 6, 2001, Pages 312-317

  Chew, K W ^a   Yeo, K S ^a   Chu, S F ^a   Wang, Y M ^a  

^a CHARTERED SEMICONDUCTOR MANUFACTURING LTD   (Singapore)

Author keywords

[No Author keywords available]

Indexed keywords

CMOS INTEGRATED CIRCUITS; COMPUTER SIMULATION; INTEGRATED CIRCUIT MANUFACTURE; INTERFACES (MATERIALS); MATHEMATICAL MODELS; MOSFET DEVICES; SPURIOUS SIGNAL NOISE;

DUAL-THICKNESS GATE OXIDE TECHNOLOGY; FLICKER NOISE; SOFTWARE PACKAGE HSPICE;

GATES (TRANSISTOR);

EID: 0035707060     PISSN: 13502409     EISSN: None     Source Type: Journal    
DOI: 10.1049/ip-cds:20010626     Document Type: Article

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