Architectural approaches to reducing power related system costs

IEEE Topical Meeting on Electrical Performance of Electronic Packaging

Volumn , Issue , 2001, Pages 7-8

  Gunther, Stephen H ^a  

^a INTEL CORPORATION   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

HEAT LOSSES; INTEGRATED CIRCUIT LAYOUT; MICROPROCESSOR CHIPS; NORMAL DISTRIBUTION; OPTIMIZATION; PORTABLE EQUIPMENT; RELIABILITY; TRANSISTORS;

CIRCUIT POWER CONSUMPTION; INTEGRATED CIRCUIT POWER CONSUMPTION; POWER DELIVERY NETWORK; POWER REDUCTION TECHNIQUE; THERMAL DISSIPATION;

ELECTRIC POWER SUPPLIES TO APPARATUS;

EID: 0035703522     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (0)