SI and design considerations for Gbps PCBs in communication systems

IEEE Topical Meeting on Electrical Performance of Electronic Packaging

Volumn , Issue , 2001, Pages 287-290

  Mu, Zhen ^a   Willis, Ken ^a  

^a Sycamore Networks   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

BANDWIDTH; CROSSTALK; DIELECTRIC LOSSES; ELECTRIC NETWORK TOPOLOGY; PRINTED CIRCUIT BOARDS; SIGNAL PROCESSING; SKIN EFFECT; SPURIOUS SIGNAL NOISE;

DRIVER COMPENSATION; INTERCONNECT DESIGN; LINEAR ESTIMATION; SIGNAL INTEGRITY;

PRINTED CIRCUIT DESIGN;

EID: 0035701573     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (3)

1. Power plane spice models for frequency and time domain
2. Circuit card layout considerations for 10Gbps current mode logic inputs on the MAX3905 EV Kit
3. The impact of PWB construction on high-speed signals