Mapping reference code to irregular DSPs within the retargetable, optimizing compiler COGEN(T)

Proceedings of the Annual International Symposium on Microarchitecture

Volumn , Issue , 2001, Pages 192-202

  Gréwal, Gary William ^a   Wilson, Charles Thomas ^a  

^a UNIVERSITY OF GUELPH   (Canada)

Author keywords

[No Author keywords available]

Indexed keywords

DIGITAL-SIGNAL PROCESSORS (DSP);

APPLICATION SPECIFIC INTEGRATED CIRCUITS; CODE CONVERTERS; CODES (SYMBOLS); COMPUTER ARCHITECTURE; DIGITAL SIGNAL PROCESSING; EMBEDDED SYSTEMS; GENETIC ALGORITHMS; OPTIMIZATION;

PROGRAM COMPILERS;

EID: 0035696720     PISSN: 10724451     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/MICRO.2001.991118     Document Type: Conference Paper

References (11)

1. Optimal code generation for embedded memory non-homogeneous register architectures
2. Chess: Retargetable code generation from embedded DSP processors
3. CodeSyn: A retargetable code synthesis system
4. An ILP-based approach to code generation
5. An enhanced genetic algorithm for solving the high-level synthesis problems of scheduling, allocation, and binding
6. An enhanced genetic algorithm for solving constraint-satisfaction problems