Space and time compaction schemes for embedded cores

IEEE International Test Conference (TC)

Volumn , Issue , 2001, Pages 521-529

  Sinanoglu, Ozgur ^a   Orailoglu, Alex ^a  

^a UNIVERSITY OF CALIFORNIA   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

BANDWIDTH; COMBINATORIAL CIRCUITS; EMBEDDED SYSTEMS; SEQUENTIAL CIRCUITS;

COMPACTOR CIRCUITRY; TEST ACCESS MECHANISM;

CHIP SCALE PACKAGES;

EID: 0035684147     PISSN: 10893539     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (14)

1. A structured and scalable mechanism for test access to embedded reusable cores
2. Testing embedded-core based system chips
3. Test requirements for embedded core-based systems and IEEE P1500
4. A structured test re-use methodology for core-based system chips
5. Space compaction methods with output data modification
6. Space compression method for built-in self-testing of VLSI circuits
7. Programmable BIST space compactors
8. Optimal space compaction of test responses
9. Zero-aliasing space compaction using linear compactors with bounded overhead
10. Zero-aliasing space compression using a single periodic output and its application to testing of embedded cores
11. Test response compaction using multiplexed parity trees
12. Heuristic solutions for the general maximum independent set problem with applications to expert system design
13. A neural netlist of 10 combinational benchmark designs and a special translator in fortran