Fast IP packet classification with configurable processor

Conference Record / IEEE Global Telecommunications Conference

Volumn 4, Issue , 2001, Pages 2268-2274

  Ji, H Michael ^a   Carchia, Michael ^a  

^a Tensilica Inc   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

APPLICATION SPECIFIC INTEGRATED CIRCUITS; CACHE MEMORY; COMPUTER ARCHITECTURE; INTERNET; NETWORK PROTOCOLS; PROGRAM PROCESSORS; QUALITY OF SERVICE; REDUCED INSTRUCTION SET COMPUTING; ROUTERS; TABLE LOOKUP;

CONFIGURABLE PROCESSORS; PACKET CLASSIFICATION;

PACKET NETWORKS;

EID: 0035681470     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (12)

1. Space decomposition techniques for fast layer-4 switching
2. Tradeoffs for packet classification
3. Packet classification on multiple fields
4. Dynamic algorithms with worst-case performance for packet classification
5. Fast IP routing lookup with configurable processor and compressed routing table
6. High-speed policy-based packet forwarding using efficient multidimensional range matching
7. Faster IP lookups using controlled prefix expansion
8. Scalable level 4 switching and fast firewall processing
9. Fast packet classification using tuple space search
10. A modular approach to packet classification: Algorithms and results