Testing gigabit multilane SerDes interfaces with passive jitter injection filters

IEEE International Test Conference (TC)

Volumn , Issue , 2001, Pages 297-304

  Laquai, Bernd ^a   Cai, Yi ^b  

^a AGILENT TECHNOLOGIES   (Germany)

^b AGERE SYSTEMS   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

BANDWIDTH; BIT ERROR RATE; COMPUTER ARCHITECTURE; JITTER; PASSIVE FILTERS;

DATA LINKS; PASSIVE JITTER INJECTION FILTERS;

INTERFACES (COMPUTER);

EID: 0035680882     PISSN: 10893539     EISSN: None     Source Type: Journal    
DOI: 10.1109/TEST.2001.966645     Document Type: Article

References (5)

1. Fibre channel - Methodologies for Jitter specification
2. Digital serial communication device testing and its implications on automatic test equipment architecture