A novel approach to high-level switching activity modeling with applications to low-power DSP system synthesis

IEEE Transactions on Signal Processing

Volumn 49, Issue 12, 2001, Pages 3157-3167

  Lundberg, Magnus ^b   Muhammad, Khurram ^c   Roy, Kaushik ^a,d   Wilson, Sarah Kate ^a,e  

^a IEEE

^b CHALMERS UNIVERSITY OF TECHNOLOGY   (Sweden)

^c TEXAS INSTRUMENTS   (United States)

^d PURDUE UNIVERSITY   (United States)

^e ArrayComm LLC   (United States)

Author keywords

High level modeling; Input reordering; Low power synthesis; Power estimation; Switching activity

Indexed keywords

ADDERS; COMPUTER AIDED DESIGN; COMPUTER AIDED SOFTWARE ENGINEERING; COMPUTER SIMULATION; ELECTRIC POTENTIAL; HIERARCHICAL SYSTEMS; MULTIPLYING CIRCUITS; SWITCHING SYSTEMS;

POWER ESTIMATION;

DIGITAL SIGNAL PROCESSING;

EID: 0035676883     PISSN: 1053587X     EISSN: None     Source Type: Journal    
DOI: 10.1109/78.969522     Document Type: Article

References (15)

1. Low-power CMOS digital design
2. Power estimation for high level synthesis
3. Analytical estimation of transition activity from word-level signal statistics
4. Toward a high-level power estimation capability
5. High-level power estimation of VLSI systems
6. Power macromodeling for high level power estimation
7. A survey of power estimation techniques in VLSI circuits
8. Switching characteristics of generalized army multiplier architectures and their applications to low power design