Formal modeling and verification in the software engineering framework of IEC61499: A way to self-verifying systems

IEEE International Conference on Emerging Technologies and Factory Automation, ETFA

Volumn 2, Issue , 2001, Pages 113-118

  Vyatkin, Valeriy ^a   Hanisch, Hans Michael ^a  

^a MARTIN LUTHER UNIVERSITY HALLE WITTENBERG   (Germany)

Author keywords

[No Author keywords available]

Indexed keywords

NET CONDITION EVENT SYSTEMS; SELF-VERIFYING SYSTEMS; SOFTWARE PACKAGE VERIFICATION ENVIRONMENT FOR DISTRIBUTED APPLICATIONS;

AGILE MANUFACTURING SYSTEMS; COMPUTER ARCHITECTURE; COMPUTER SIMULATION; DISTRIBUTED COMPUTER SYSTEMS; GRAPHICAL USER INTERFACES; MATHEMATICAL MODELS; SOFTWARE ENGINEERING;

NETWORK PROTOCOLS;

EID: 0035557305     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (10)

1. Automatic verification of finite state concurrent systems using temporal logic
2. Bringing the model-based verification of distributed control systems into the engineering practice
3. VEDA - A prototype tool for deep debugging of distributed applications
4. A modeling approach for verification of IECI499 function blocks using net condition/event systems
5. Practice of modeling and verification of distributed controllers using signal-net systems