Threshold voltage spread in flash memories under a constant ΔQ erasing scheme

Microelectronic Engineering

Volumn 59, Issue 1-4, 2001, Pages 197-201

  Chimenton, Andrea ^a   Pellati, Paolo ^a   Olivo, Piero ^a  

^a UNIVERSITY OF FERRARA   (Italy)

Author keywords

Erasing operations; Flash memories; Integrated circuit reliability; Reliability; Semiconductor memories

Indexed keywords

ELECTRIC CHARGE; INTEGRATED CIRCUIT LAYOUT; NONVOLATILE STORAGE; THRESHOLD VOLTAGE;

INTEGRATED CIRCUIT RELIABILITY;

FLASH MEMORY;

EID: 0035498474     PISSN: 01679317     EISSN: None     Source Type: Journal    
DOI: 10.1016/S0167-9317(01)00622-0     Document Type: Conference Paper

References (4)

1. Modelling of write/erase and charge retention characteristics of floating gate EEPROM devices
2. Analysis and modeling of floating-gate EEPROM cells
3. Analysis of erratic bits in Flash memories
4. Physical aspects of cell operation and reliability