Charge-mode parallel architecture for vector-matrix multiplication

IEEE Transactions on Circuits and Systems II: Analog and Digital Signal Processing

Volumn 48, Issue 10, 2001, Pages 930-936

  Genov, Roman ^a,b   Cauwenberghs, Gert ^a,b  

^a IEEE   (United States)

^b Johns Hopkins University   (United States)

Author keywords

Analog array processors; Analog to digital conversion (ADC); Charge injection device (CID); Dynamic random access memory (DRAM); Support vector machines (SVM); Vector quantization (VQ); Vector matrix multiplication (VMM)

Indexed keywords

ANALOG ACCUMULATOR; ANALOG ARRAY PROCESSORS; CHARGE INJECTION DEVICE; SUPPORT VECTOR MACHINES; VECTOR MATRIX MULTIPLICATION;

ANALOG TO DIGITAL CONVERSION; CMOS INTEGRATED CIRCUITS; DYNAMIC RANDOM ACCESS STORAGE; PROGRAM PROCESSORS; VECTOR QUANTIZATION;

MULTIPLYING CIRCUITS;

EID: 0035493792     PISSN: 10577130     EISSN: None     Source Type: Journal    
DOI: 10.1109/82.974781     Document Type: Article

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