A 2-D analytical threshold voltage model for fully-depleted SOI MOSFETs with halos or pockets

IEEE Transactions on Electron Devices

Volumn 48, Issue 10, 2001, Pages 2292-2302

  Van Meer, Hans ^a,b   De Meyer, Kristin ^a,b  

^a IEEE   (Belgium)

^b IMEC   (Belgium)

Author keywords

Modeling; MOS devices; MOSFETs

Indexed keywords

FULLY-DEPLETED SOI MOSFETS; HALOS; TWO DIMENSIONAL ANALYTICAL THRESHOLD VOLTAGE MODEL;

COMPUTER SIMULATION; CURRENT DENSITY; ELECTRIC FIELDS; FOURIER TRANSFORMS; GREEN'S FUNCTION; MOS DEVICES; POISSON EQUATION; SILICA; SILICON ON INSULATOR TECHNOLOGY; THRESHOLD VOLTAGE;

MOSFET DEVICES;

EID: 0035472153     PISSN: 00189383     EISSN: None     Source Type: Journal    
DOI: 10.1109/16.954468     Document Type: Article

References (15)

1. 0.18-μm fully-depleted silicon-on-insulator MOSFETs
2. A 0.18 μm fully-depleted CMOS on 30 nm thick SOI for sub-1.0 V operation
3. 0.18 μm metal gate fully-depleted SOI MOSFETs for advanced CMOS applications
4. Thin-film SOI technology: The solution to many submicron CMOS problems
5. Short-channel effects in SOI MOSFETs
6. Short-channel effects in fully depleted SOI MOSFETs
7. Two-dimensional analytic modeling of very thin SOI MOSFETs
8. A new 2-D analytic threshold-voltage model for fully-depleted short-channel SOI MOSFETs
9. Halo doping effects in submicron DI-LDD device design
10. A 0.1-μm CMOS technology with tilt-implanted punchthrough stopper (TIPS)
11. A new approach to analytically solving the 2-D Poisson's equation and its application in short-channel MOSFET modeling
12. A new two-dimensional model for the potential distribution of short gate-length MESFETs and its applications
13. Buried oxide fringing capacitance: A new physical model and its implication on SOI device scaling and architecture