Ultra-thinning of C4 integrated circuits for backside analysis during first silicon debug

Microelectronics Reliability

Volumn 41, Issue 9-10, 2001, Pages 1545-1549

  Lundquist, T ^a   Delenia, E ^a   Harroun, J ^a   Leroy, E ^a   Tsao, C C ^a  

^a SCHLUMBERGER   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

FAILURE ANALYSIS; SEMICONDUCTING SILICON; SUBSTRATES; THICKNESS CONTROL;

SILICON DEBUG;

INTEGRATED CIRCUIT TESTING;

EID: 0035456845     PISSN: 00262714     EISSN: None     Source Type: Journal    
DOI: 10.1016/S0026-2714(01)00171-8     Document Type: Article

References (8)

1. th International Symposium for Testing and Failure Analysis, 317(1999).
2. R. Livengood and V. Rao, Semiconductor International, March (1998) 111.
3. th International Symposium for Testing and Failure Analysis (1998) 459.
4. th International Reliability Physics Symposium (1999) 22.
5. R Livengood, P Winer, V Rao, JVST B (1999) 40.
6. th International Symposium for Testing and Failure Analysis, 35 (1999).
7. M. Sengupta, M. Sinha, G. Dajee, C.-C. Tsao, to be published in JVST B (Nov/Dec, 2001).
8. M. Potter, private communication (2001).