Searching for critical gates in logic synthesis

Shanghai Jiaotong Daxue Xuebao/Journal of Shanghai Jiaotong University

Volumn 35, Issue 9, 2001, Pages 1275-1279+1302

  Zhang, Lei ^a   Lin, Zheng Hui ^a   Lu, Zong Wei ^a  

^a SHANGHAI JIAO TONG UNIVERSITY   (China)

Author keywords

Critical path; FAN algorithm; Sensitization; Timing optimization

Indexed keywords

ALGORITHMS; DELAY CIRCUITS; INTEGRATED CIRCUIT LAYOUT; LOGIC DESIGN; LOGIC GATES;

CRITICAL PATH; TIMING OPTIMIZATION;

NETWORKS (CIRCUITS);

EID: 0035453541     PISSN: 10062467     EISSN: None     Source Type: Journal    
DOI: None     Document Type: Article

References (6)

1. Computation of floating mod delay in combinational circuits: Theory and algorithms
2. On the general false path problem in timing analysis
3. Timing verification and the timing analysis problem
4. Path sensitization in critical path problem
5. Controllability/observability analysis of digital circuits