SCOPUS 정보 검색 플랫폼

Volumn 18, Issue 7, 2001, Pages 36-40+42

The SDM test method: Past, present, and future

(6) Chaine, M a Barth, J a Brodbeck, T a Henry, L G a Kelly, M A a Meuse, T a

Author keywords

[No Author keywords available]

Indexed keywords

CAPACITANCE; COMPUTER SIMULATION; ELECTRIC CONNECTORS; ELECTRIC DISCHARGES; ELECTRIC POWER SUPPLIES TO APPARATUS; ELECTRONICS PACKAGING; ELECTROSTATICS; INDUCTANCE; INTEGRATED CIRCUIT LAYOUT; MATHEMATICAL MODELS; WAVEFORM ANALYSIS;

CHARGED DEVICE MODEL; ELECTROSTATIC DISCHARGE; HIGH VOLTAGE POWER SUPPLY; SOCKETED DEVICE MODEL;

INTEGRATED CIRCUIT TESTING;

EID: 0035448366 PISSN: 08983577 EISSN: None Source Type: Trade Journal
DOI: None Document Type: Article

Times cited : (3)

References (16)

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2
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4
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5
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6
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- EOS/ESD-CDM-WIP5.3-1994; ESD Association, Rome, NY

7
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8
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9
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- Brodbeck, T.¹

10
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- Verhaege, K.¹

11
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- NMOS transistor behavior under CDM stress conditions and relation to other models
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12
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13
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14
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15
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16
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* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.