Feasibility of 0.18 μm SOI CMOS technology using hybrid trench isolation with high resistivity substrate for embedded RF/analog applications

IEEE Transactions on Electron Devices

Volumn 48, Issue 9, 2001, Pages 2065-2073

  Maeda, Shigenobu ^b   Wada, Yoshiki ^b   Yamamoto, Kazuya ^a   Komurasaki, Hiroshi ^b   Matsumoto, Takuji ^b   Hirano, Yuuichi ^b   Iwamatsu, Toshiaki ^b   Yamaguchi, Yasuo ^b   Ipposhi, Takashi ^b   Ueda, Kimio ^b   Mashiko, Koichiro ^b   Maegawa, Shigeto ^b   Inuishi, Masahide ^b  

^a IEEE

^b MITSUBISHI ELECTRIC CORPORATION   (Japan)

Author keywords

Analog circuits; Inductors; Metal oxide semiconductor field effect transistor (MOSFET); Noise measurement; Silicon on insulator technology (SOI); Wireless LAN

Indexed keywords

ALUMINUM; ELECTRIC CONDUCTIVITY OF SOLIDS; GATES (TRANSISTOR); MOSFET DEVICES; SEMICONDUCTOR DEVICE STRUCTURES; SILICON ON INSULATOR TECHNOLOGY; SPURIOUS SIGNAL NOISE; SUBSTRATES;

ANALOG CIRCUIT; HIGH RESISTIVITY SUBSTRATE;

CMOS INTEGRATED CIRCUITS;

EID: 0035444844     PISSN: 00189383     EISSN: None     Source Type: Journal    
DOI: 10.1109/16.944197     Document Type: Article

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