SCOPUS 정보 검색 플랫폼

IEEE Design and Test of Computers

Volumn 18, Issue 5, 2001, Pages 92-99

Online and offline BIST in IP-core design

(5) Benso, Alfredo a Chiusano, Silvia a Di Natale, Giorgio a Prinetto, Paolo a Bodoni, Monica Lobetti b

a POLITECNICO DI TORINO (Italy)

b Siemens Information and Communication Networks ^*

Author keywords

[No Author keywords available]

Indexed keywords

FAULT-LATENCY REDUCTION;

ASYNCHRONOUS TRANSFER MODE; CODING ERRORS; CONSTRAINT THEORY; DATA STORAGE EQUIPMENT; INTEGRATED CIRCUIT TESTING; INTELLECTUAL PROPERTY; ONLINE SYSTEMS; STATIC RANDOM ACCESS STORAGE;

BUILT-IN SELF TEST;

EID: 0035444246 PISSN: 07407475 EISSN: None Source Type: Journal
DOI: 10.1109/54.953276 Document Type: Article

Times cited : (5)

References (10)

1
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- Nicolaidis, M.¹ Zorian, Y.²

2
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- John Wiley & Sons, Chichester, UK
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- Van de Goor, A.J.¹

3
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- Online BIST for embedded systems
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- (1998) IEEE Design & Test of Computers , vol.15 , Issue.4 , pp. 17-24
- Al-Asaad, H.¹ Murray, B.T.² Hayes, J.P.³

4
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- An on-line BISTed RAM architecture with self-repair capabilities
- Sept.-Oct.
- (2001) IEEE Trans. Reliability
- Benso, A.¹

5
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- An on-line BISTed SRAM IP-Core
- IEEE CS Press, Los Alamitos, Calif.
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- Benso, A.¹

6
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- Using march tests to test SRAMs
- Mar.
- (1993) IEEE Design & Test of Computers , vol.10 , Issue.1 , pp. 8-14
- Van de Goor, A.J.¹

7
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- North-Holland Mathematical Library, North-Holland, Amsterdam
- (1998) The Theory of Error-Correcting Codes II , vol.16
- Macwilliams, F.J.¹ Sloane, N.J.A.²

8
- 84893810610
- March tests for word-oriented memories
- IEEE CS Press, Los Alamitos, Calif.
- (1998) Proc. IEEE Design Automation and Test in Europe , pp. 501-508
- Van de Goor, A.J.¹ Tilli, I.B.S.²

9
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- Morgan Kaufmann, San Mateo, Calif.
- (2001) Self-Checking and Fault-Tolerant Digital Design
- Lala, P.K.¹

10
- 0003858620
- IEEE Std 1149.1-1990, IEEE Press, Piscat-away, N.J.
- (1993) Test Access Port and Boundary-Scan Architecture

* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.