SCOPUS 정보 검색 플랫폼

Analog Integrated Circuits and Signal Processing

Volumn 28, Issue 3, 2001, Pages 239-252

Limitations of the MOS resistive circuit in MOSFET-C implementation: Bandwidth, noise, offset and non-linearity

(2) Osa, J I a Carlosena, Alfonso a

a PUBLIC UNIVERSITY OF NAVARRE (Spain)

Author keywords

Double MOSFET; Four transistor transconductor; MOS resistive circuit; MOSFET C circuits; RC active circuits

Indexed keywords

BANDWIDTH; COMPUTER SIMULATION; FREQUENCY RESPONSE; MATHEMATICAL MODELS; MOS DEVICES; MOSFET DEVICES; OPERATIONAL AMPLIFIERS; RESISTORS; SIGNAL DISTORTION; SPURIOUS SIGNAL NOISE; TRANSCONDUCTANCE;

FOUR-TRANSISTOR TRANSCONDUCTOR; MOS RESISTIVE CIRCUIT; MOSFET-C CIRCUITS; SOFTWARE PACKAGE BSIM3;

ACTIVE NETWORKS;

EID: 0035438955 PISSN: 09251030 EISSN: None Source Type: Journal
DOI: 10.1023/A:1011251910102 Document Type: Article

Times cited : (1)

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* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.