Model of low frequency noise in polycrystalline silicon thin-film transistors

IEEE Electron Device Letters

Volumn 22, Issue 8, 2001, Pages 381-383

  Dimitriadis, Charalabos A ^a,b   Kamarinos, George ^c   Brini, Jean ^c  

^a IEEE   (Greece)

^b ARISTOTLE UNIVERSITY OF THESSALONIKI   (Greece)

^c Grenoble INP Phelma   (France)

Author keywords

Grain boundary traps; Low frequency noise; Oxide traps; Polysilicon TFTs

Indexed keywords

POTENTIAL BARRIER;

ELECTRON CYCLOTRON RESONANCE; GATES (TRANSISTOR); GRAIN BOUNDARIES; MOSFET DEVICES; PLASMA ENHANCED CHEMICAL VAPOR DEPOSITION; POLYSILICON; SPURIOUS SIGNAL NOISE; THRESHOLD VOLTAGE;

THIN FILM TRANSISTORS;

EID: 0035423462     PISSN: 07413106     EISSN: None     Source Type: Journal    
DOI: 10.1109/55.936350     Document Type: Article

References (10)

1. Large 1/f noise in polysilicon TFT loads and its effects on the stability of SRAM cells
2. Evidence of carrier number fluctuation as origin of 1/f noise in polycrystalline silicon thin film transistors
3. Noise performances in polycrystalline silicon thin-film transistors fabricated by excimer laser crystallization
4. Dimension scaling of low frequency noise in the drain current of polycrystalline silicon thin film transistors
5. Conductivity behavior in polycrystalline semiconductor thin-film transistors
6. The electrical properties of polycrystalline silicon films
7. Subthreshold slope in polycrystalline silicon thin-film transistors and effect of the gate oxide on the subthreshold characteristics
8. On the theory of carrier number fluctuations in MOS devices
9. Excimer laser annealing of amorphous and solid-phase-crystallized silicon films
10. Field-effect conductance activation energy in an undoped polycrystalline silicon thin-film transistor