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Semiconductor Science and Technology

Volumn 16, Issue 8, 2001, Pages 641-650

Interfacial charge trapping in extrinsic Y2O3/SiO2 bilayer gate dielectric based MIS devices on Si(100)

(2) Rastogi, A C a Sharma, R N a,b

a NATIONAL PHYSICAL LABORATORY (India)

b Usha India Limited (India)

Author keywords

[No Author keywords available]

Indexed keywords

ANNEALING; CURRENT VOLTAGE CHARACTERISTICS; DIELECTRIC FILMS; ELECTRON TRAPS; HYSTERESIS; INTERFACES (MATERIALS); LEAKAGE CURRENTS; PERMITTIVITY; SEMICONDUCTING SILICON; SEMICONDUCTOR DEVICE STRUCTURES; SILICA; YTTRIUM COMPOUNDS;

ACCUMULATION-INVERSION MODE; CAPACITANCE-VOLTAGE BEHAVIOUR; INTERFACIAL CHARGE TRAPPING; INTERFACIAL SILICA; MID-GAP INTERFACE STATE;

MIS DEVICES;

EID: 0035421145 PISSN: 02681242 EISSN: None Source Type: Journal
DOI: 10.1088/0268-1242/16/8/301 Document Type: Article

Times cited : (32)

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