A low-noise, low-power CMOS SOI readout front-end for silicon detectors leakage current compensation with capability

IEEE Transactions on Circuits and Systems I: Fundamental Theory and Applications

Volumn 48, Issue 8, 2001, Pages 1022-1030

  Hu, Y ^a   Deptuch, G ^b   Turchetta, R ^a   Guo, C ^c  

^a CENTRE DE CALCUL DE L INSTITUT NATIONAL DE PHYSIQUE NUCLEAIRE ET DE PHYSIQUE DES PARTICULES   (France)

^b AGH UNIVERSITY OF SCIENCE AND TECHNOLOGY   (Poland)

^c INSTITUT DE RECHERCHES SUBATOMIQUES   (France)

Author keywords

Low noise CMOS preamplifiers; Noise optimization sensor interface circuits

Indexed keywords

AMPLIFIERS (ELECTRONIC); CAPACITANCE; COUPLED CIRCUITS; LEAKAGE CURRENTS; SENSORS; SILICON ON INSULATOR TECHNOLOGY; SPURIOUS SIGNAL NOISE;

EQUIVALENT NOISE CHARGE (ENC);

CMOS INTEGRATED CIRCUITS;

EID: 0035417865     PISSN: 10577122     EISSN: None     Source Type: Journal    
DOI: 10.1109/81.940194     Document Type: Article

References (10)

1. Limits of low noise performance of detector readout front ends in CMOS technology
2. ICON, a current mode preamplifier in CMOS technology for use with high rate particle detectors
3. Current mode charge pulse amplifier in CMOS technology for use with particle detectors
4. Pixel detectors with local intelligence: An IC designer point of view
5. A very low-power, low-noise analog readout chip for capacitive detectors with a power supply of 3.3 V
6. Study of a CMOS-JFET-bipolar radiation hard analog-digital technology suitable for high energy physics electronics