Cost minimization and workload balancing in printed circuit board assembly

IIE Transactions (Institute of Industrial Engineers)

Volumn 33, Issue 7, 2001, Pages 547-557

  Hillier, Mark S ^a   Brandeau, Margaret L ^b  

^a UNIVERSITY OF WASHINGTON   (United States)

^b Stanford University   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

COST EFFECTIVENESS; FACTORY AUTOMATION; FLEXIBLE MANUFACTURING SYSTEMS; HEURISTIC METHODS; INTEGER PROGRAMMING; MACHINERY; OPTIMIZATION; SCHEDULING;

BINARY INTEGER PROGRAM; COST MINIMIZING WORKLOAD BALANCING; OPERATION ASSIGNMENT PROBLEM; PRINTED CIRCUIT BOARD ASSEMBLY;

PRINTED CIRCUIT MANUFACTURE;

EID: 0035400757     PISSN: 0740817X     EISSN: None     Source Type: Journal    
DOI: 10.1080/07408170108936853     Document Type: Article

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