Current mirror layout strategies for enhancing matching performance

Analog Integrated Circuits and Signal Processing

Volumn 28, Issue 1, 2001, Pages 9-26

  Lan, Mao Feng ^a   Tammineedi, Anilkumar ^a   Geiger, Randall ^a  

^a Iowa State University   (United States)

Author keywords

Current mirror layout strategies; Linear parameter gradients; Matching performance

Indexed keywords

CMOS INTEGRATED CIRCUITS; COMPUTER SIMULATION; ELECTRIC CURRENTS; ELECTRIC IMPEDANCE; INTEGRAL EQUATIONS; LINEAR INTEGRATED CIRCUITS; PATTERN MATCHING; THRESHOLD VOLTAGE; TRANSISTORS;

CURRENT MIRROR LAYOUT; LINEAR PARAMETER GRADIENT;

INTEGRATED CIRCUIT LAYOUT;

EID: 0035400423     PISSN: 09251030     EISSN: None     Source Type: Journal    
DOI: 10.1023/A:1011237602078     Document Type: Article

References (5)

1. Matching properties of MOS transistors
2. Characterization and modeling of mismatch in MOS transistors for precision analog design
3. Measurement and modeling of MOS transistor current mismatch in analog IC's
4. Manufacturability of low power CMOS technology solutions
5. Matching performance of current mirrors with arbitrary parameter gradients through the active devices