T BD prediction from low-voltage near-interface trap-assisted tunneling current measurements

IEEE Transactions on Electron Devices

Volumn 48, Issue 7, 2001, Pages 1354-1359

  Ghetti, Andrea ^a,b   Bude, Jeff ^a,c   Weber, Gary ^c  

^a IEEE   (Italy)

^b STMICROELECTRONICS   (Italy)

^c LUCENT TECHNOLOGIES   (United States)

Author keywords

Interface traps; Low voltage tunneling; Oxide reliability

Indexed keywords

STRESS INDUCED LEAKAGE CURRENTS (SILC);

ELECTRON TRAPS; ELECTRON TUNNELING; EXTRAPOLATION; LEAKAGE CURRENTS; SEMICONDUCTOR DOPING;

MOS DEVICES;

EID: 0035395763     PISSN: 00189383     EISSN: None     Source Type: Journal    
DOI: 10.1109/16.930651     Document Type: Article

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