High field stress at and above room temperature in 2.3 nm thick oxides

Microelectronics Reliability

Volumn 41, Issue 7, 2001, Pages 1023-1026

  Zander, D ^a   Petit, C ^a   Saigne, F ^a   Meinertzhagen, A ^a  

^a UNIVERSITÉ DE REIMS CHAMPAGNE ARDENNE   (France)

Author keywords

[No Author keywords available]

Indexed keywords

DEGRADATION; ELECTRIC CURRENTS; GATES (TRANSISTOR); OXIDES; STRESS ANALYSIS; SUBSTRATES; THERMOANALYSIS;

THICK OXIDES;

MOSFET DEVICES;

EID: 0035394885     PISSN: 00262714     EISSN: None     Source Type: Journal    
DOI: 10.1016/S0026-2714(01)00062-2     Document Type: Article

References (10)

1. 2 films
2. Correlation of stress-induced leakage current in thin oxides with trap generation inside the oxides
3. Mechanism of stress-induced leakage current in MOS capacitors
4. Modeling of SILC based on electron and hole tunneling - Part II: Steady-state
5. Low voltage tunneling in ultra-thin oxides: A monitor for interface states and degradation
6. Electrical stress effects on ultra-thin (2.3 nm) oxides
7. 2 films
8. Investigation of temperature acceleration of thin oxide time-to-breakdown
9. Oxide scaling limit for future logic and memory technology
10. 2 oxide <5 nm thick films