SCOPUS 정보 검색 플랫폼

IEEE Design and Test of Computers

Volumn 18, Issue 4, 2001, Pages 46-55

Optimizing multiple EDA tools within the ASIC design flow

(2) Bening, Lionel a Foster, Harry a

a HEWLETT PACKARD COMPANY (United States)

Author keywords

[No Author keywords available]

Indexed keywords

DATA HIDING; ELECTRONIC DESIGN OPTIMIZATION (EDA); REGISTER-TRANSFER LEVEL (RTL) CODING;

AUTOMATION; COMPUTER AIDED LOGIC DESIGN; COMPUTER HARDWARE DESCRIPTION LANGUAGES; FLIP FLOP CIRCUITS; HIGH LEVEL LANGUAGES; INTEGRATED CIRCUIT LAYOUT; MACROS; OPTIMIZATION; VLSI CIRCUITS;

COMPUTER AIDED SOFTWARE ENGINEERING;

EID: 0035394339 PISSN: 07407475 EISSN: None Source Type: Journal
DOI: 10.1109/54.936248 Document Type: Article

Times cited : (1)

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* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.