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Volumn 18, Issue 4, 2001, Pages 56-64
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A two-input, one-output bit-scalable architecture for fuzzy processors
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ITA
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Author keywords
[No Author keywords available]
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Indexed keywords
FUZZY PROCESSORS;
INFERENCE PROCESSES;
BOOLEAN ALGEBRA;
COMPUTER ARCHITECTURE;
COMPUTER SIMULATION;
FIELD PROGRAMMABLE GATE ARRAYS;
FUZZY CONTROL;
INFERENCE ENGINES;
LOGIC CIRCUITS;
MATRIX ALGEBRA;
MEMBERSHIP FUNCTIONS;
PROGRAM PROCESSORS;
RANDOM ACCESS STORAGE;
REAL TIME SYSTEMS;
MICROCONTROLLERS;
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EID: 0035393234
PISSN: 07407475
EISSN: None
Source Type: Journal
DOI: 10.1109/54.936249 Document Type: Article |
Times cited : (23)
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References (10)
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