Hough transform algorithm for FPGA implementation

Signal Processing

Volumn 81, Issue 6, 2001, Pages 1295-1301

  Tagzout, Samir ^a   Achour, Karim ^a   Djekoune, Oualid ^a  

^a CENTRE DE DÉVELOPPEMENT DES TECHNOLOGIES AVANCÉES   (Algeria)

Author keywords

FPGA; Hough transform; Image processing

Indexed keywords

ALGORITHMS; FIELD PROGRAMMABLE GATE ARRAYS; IMAGE ANALYSIS; IMAGE QUALITY; VLSI CIRCUITS;

GENERATOR PROGRAMS;

HOUGH TRANSFORMS;

EID: 0035369768     PISSN: 01651684     EISSN: None     Source Type: Journal    
DOI: 10.1016/S0165-1684(00)00248-6     Document Type: Article

References (16)

1. Pipelined implementation of the multiresolution Hough transform in a pyramid multiprocessor
2. Synchronous multiprocessor implementation of the Hough transform
3. Analogue implementation of the Hough transform
4. Constant coefficient multipliers
5. Implementation and evaluation of Hough transform algorithm on a shared-memory multiprocessor
6. Using Canny's criteria to deliver an implementated optimal edge detector
7. Using FPGAs in digital signal processing application
8. A survey of the Hough transform
9. FIHT2 Algorithm: A fast incremental Hough transform
10. Hough transform for transputer arrays
11. A comparaison of Hough transform methods
12. Compact parallel multipliers using the sign-generate method in FPGA
13. Implementation of the 2D DCT using a Xilinx XC6264 FPGA
14. Deriving ASIC architectures for the Hough transform