A high-efficiency thin-film SOI power MOSFET having a self-aligned offset gate structure for multi-gigahertz applications

IEEE Transactions on Electron Devices

Volumn 48, Issue 6, 2001, Pages 1270-1273

  Matsumoto, S ^a   Hiraoka, Y ^a   Sakai, T ^a  

^a NTT CORPORATION   (Japan)

Author keywords

Power MOSFET; SOI technology

Indexed keywords

ELECTRIC BREAKDOWN; GATES (TRANSISTOR); SEMICONDUCTOR DOPING; SILICON ON INSULATOR TECHNOLOGY; THIN FILM TRANSISTORS;

LIGHTLY DOPED DRAIN (LDD) STRUCTURES;

MOSFET DEVICES;

EID: 0035367875     PISSN: 00189383     EISSN: None     Source Type: Journal    
DOI: 10.1109/16.925259     Document Type: Article

References (8)

1. A highly efficient 1.9-GHz Si high-power MOS amplifier
2. High-efficiency 2 GHz power Si-MOSFET design under low supply voltage
3. Highly efficient 1.5 GHz Si power MOSFET for digital cellular front end
4. An SOI-RF-CMOS technology on high-resistivity SIMOX substrates for microwave applications to 5 GHz
5. A highly-efficient tungsten-polycide gate radio-frequency power metal-oxide-semiconductor field-effect-transistor using bonded silicon-on-insulator technology
6. High efficiency LDMOS power FET for low voltage wireless communications
7. A novel high-frequency quasi-SOI power MOSFET for multi-gigahertz applications
8. Device characteristics of a 30-V-class thin-film SOI power MOSFET