PreFPIX2: Core architecture and results

IEEE Transactions on Nuclear Science

Volumn 48, Issue 3 I, 2001, Pages 485-492

  Hoff, James R ^a,b   Mekkaoui, Abder ^a,b   Christian, David C ^b   Zimmerman, Sergio ^a,b   Cancelo, Gustavo ^a,b   Kasper, Penny ^b   Yarema, Ray ^a,b  

^a IEEE   (United States)

^b FERMI NATIONAL ACCELERATOR LABORATORY   (United States)

Author keywords

Deep submicron CMOS; Pixel electronics; Radiation tolerant VLSI design

Indexed keywords

DEEP SUBMICRON TECHNOLOGY; PIXEL ELECTRONICS;

ALGORITHMS; COMPUTER SIMULATION; DATA TRANSFER; MONTE CARLO METHODS; READOUT SYSTEMS; VLSI CIRCUITS;

CMOS INTEGRATED CIRCUITS;

EID: 0035355204     PISSN: 00189499     EISSN: None     Source Type: Journal    
DOI: 10.1109/23.940104     Document Type: Conference Paper

References (7)

1. High readout speed chip developed at Fermilab
2. Development of a pixel readout chip for BTeV
3. Radiation tolerance beyond 10 Mrad for a pixel readout chip in standard submicron CMOS
4. 30 MRad (SiO2) radiation tolerant pixel front end for the BTeV experiment
5. MCFast: A fast simulation package for detector design studies