The physics of determining chip reliability

IEEE Circuits and Devices Magazine

Volumn 17, Issue 3, 2001, Pages 33-38

  Hess, K ^a   Haggag, A ^a   McMahon, W ^a   Cheng, K ^a   Lee, J ^a   Lyding, J ^a  

^a University of Illinois at Urbana Champaign   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ACTIVATION ENERGY; CARRIER MOBILITY; COST EFFECTIVENESS; FAILURE ANALYSIS; PARAMAGNETIC RESONANCE; PROBABILITY DENSITY FUNCTION; RELIABILITY THEORY; SEMICONDUCTOR DEVICE TESTING; STATISTICAL TESTS;

BOND ENERGIES;

MICROPROCESSOR CHIPS;

EID: 0035328541     PISSN: 87553996     EISSN: None     Source Type: Journal    
DOI: 10.1109/101.933789     Document Type: Article

References (18)

1. 2 defect generation in CMOS chips: From atomistic structure to chip failure rates
2. The role of the spacer oxide in determining worst-case hot-carrier stress conditions for NMOS LDD devices
3. Theory of channel hot-carrier degradation in MOSFETs
4. Decay of ultra-violet induced fiber Bragg gratings
5. High-performance chip reliability from short-time-tests: Statistical models for optical interconnect and deep-submicron transistor failures
6. b-generation-stress relationship
7. 2 interface
8. Structure, energetics, and vibrational properties of Si-H bond dissociation in silicon
9. Thermal stability of optical add/drop gratings for WDM systems
10. Hot-electron-induced MOSFET degradation-model, monitor, and improvement
11. Percolation models for gate oxide breakdown
12. 2-Si interfaces
13. 2 interface under long-term positive as well as negative bias-temperature aging
14. Bias-temperature stress on metal-oxide-semiconductor structures as compared to ionizing irradiation and tunnel injection
15. Arrhenius and the temperature dependence of non-constant failure rate
16. Constant failure rate - A paradigm in transition?