Minimizing power consumption in direct sequence spread spectrum correlators by resampling IF samples-Part II: Implementation issues

IEEE Transactions on Circuits and Systems II: Analog and Digital Signal Processing

Volumn 48, Issue 5, 2001, Pages 460-470

  Namgoong, Won ^a,b   Meng, Teresa H ^a,c  

^a IEEE   (United States)

^b University of Southern California   (United States)

^c Stanford University   (United States)

Author keywords

Correlators; Receivers; Spread spectrum communication; Synchronization

Indexed keywords

COMPUTER SIMULATION; DIGITAL SIGNAL PROCESSING; DIRECT SEQUENCE SYSTEMS; INTEGRATED CIRCUIT LAYOUT; NATURAL FREQUENCIES; SIGNAL RECEIVERS; SYNCHRONIZATION;

INTERMEDIATE FREQUENCY; POWER CONSUMPTION; RESAMPLING PARALLEL CORRELATOR; SOFTWARE PACKAGE HSPICE;

CORRELATORS;

EID: 0035327908     PISSN: 10577130     EISSN: None     Source Type: Journal    
DOI: 10.1109/82.938356     Document Type: Article

References (10)

1. A low-power CMOS chipset for spread spectrum communications
2. Low power digital CMOS design
3. A low power video-rate pyramid VQ decoder
4. Minimizing power consumption in direct sequence spread spectrum correlators by resampling IF samples-Part I: Performance analysis
5. Power reduction techniques for a spread spectrum based correlator
6. A comparison of analog and digital circuit implementations of low power matched filter for use in portable wireless communication terminals
7. ASIC design using the mentor graphics and cascade design automation tools
8. Computer-aided design of a BPSK spread-spectrum transceiver IC