70nm NMOSFET fabrication with 12 nm n+-p junctions using As2+ low energy implantations

Japanese Journal of Applied Physics, Part 1: Regular Papers and Short Notes and Review Papers

Volumn 40, Issue 4 B, 2001, Pages 2607-2610

  Choi, Byung Yong ^a,b   Sung, Suk Kang ^a,b   Park, Byung Gook ^a,b   Lee, Jong Duk ^a,b  

^a Seoul National University   (South Korea)

^b Seoul National University   (South Korea)

Author keywords

As2+ low energy implantation; Nano scale MOSFET; Shallow junction; Source drain junctions

Indexed keywords

ARSENIC; ELECTRIC RESISTANCE; GATES (TRANSISTOR); ION IMPLANTATION; RAPID THERMAL ANNEALING; SEMICONDUCTOR DOPING; SEMICONDUCTOR JUNCTIONS; THRESHOLD VOLTAGE;

LOW ENERGY IMPLANTATIONS; SHALLOW JUNCTIONS;

MOSFET DEVICES;

EID: 0035300814     PISSN: 00214922     EISSN: None     Source Type: Journal    
DOI: 10.1143/jjap.40.2607     Document Type: Article

References (7)